EDN

Using SystemVerilog for functional verification

The need to improve functional verification productivity and quality continues to grow. The 2004/2002 IC/ASIC Functional Verification Study, by Collett International Research, shows that logic or ...
EDN

SystemVerilog reference verification methodology: RTL

The SoC industry needs a reuse-oriented, coverage-driven verification methodology built on the rich semantic support of a standard language. This is the second in a series of four articles outlining a ...
Design-Reuse

System Verilog based Generic Verification Methodology for IPs/ASICs/SOCs: A Case Study

This document discusses Random constraint-based verification and explains how random verification can complement the directed verification for the generic designs. In our case this is demonstrated by ...
Design-Reuse

Design of SystemVerilog Assertion IP

SystemVerilog provides an effective means for designing assertion-based Verification IP and integrating it with a testbench. This paper explores guidelines for designing such IP within the Synopsys ...